The present invention relates to a DMA bus load varying unit.
A conventional data processing system having a DMA bus is shown in FIG. 1. A main memory 2, a central processing unit (CPU) 3, DMA units (channel) 4 and so on are connected to the DMA bus 1. Such a system is so constructed that when any of the units described above produces a request for accessing the main memory 2, the unit may acquire the DMA bus in accordance with a physically-defined priority.
In such a conventional system, a test operation has been performed on the DMA units so that any selected one of the DMA units 4 can be operated at a time. This method disables the test operation of contention among the DMA units. The actual test operation necessitates a plurality of DMA units. Furthermore, the test program should be constructed using a multiprogramming technique such that a plurality of DMA units are operated in a multiplexed manner. Still further, the test operation of the system performance such as the operation speeds of the CPU and the DMAs at the maximum load of the DMA bus also necessitates a plurality of DMA units and the multiprogramming technique. To evaluate the performance of the DMA bus, the system should be so constructed that a plurality of DMA units 4 are connected to the DMA bus to estimate each busy time of the DMA units by means of a measuring unit 5.
The measurement of the busy time will now be further described.
As is well known, when two or more DMA units connected to the DMA bus attempt to perform data transfer simultaneously, the DMA unit having lower priority must be in a waiting mode. When the DMA unit having lower priority is connected to a unit which operates in synchronism with a mechanical operation such as a magnetic disk unit, a timing error might be caused in which the next data is transferred before the previous data due to the long waiting time. Therefore, a data buffer is sometimes provided with the DMA unit to prevent a timing error. The wait time of the DMA unit is essential in order to determine the buffer size of the data buffer. Further, the above wait time is also necessary to determine an optimal system in which optimal priorities are assigned to the DMA units having different operation speeds.
In the prior art, the actual system has been constructed to evaluate the busy time of each DMA unit in accordance with the measurement from the measuring unit.